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Intel(R) 82802AB/82802AC Firmware Hub (FWH)
Datasheet
November 2000
Document Number: 290658-004
Intel 82802AB/AC Firmware Hub
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) 82802AB/AC Firmware Hub (FWH) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
2 2 I C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 *Third-party brands and names are the property of their respective owners. Copyright (c) Intel Corporation 1999-2001
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Contents
1. Architectural Overview ................................................................................................................. 9 1.1. Interface Overview........................................................................................................... 9 1.1.1. Intel Firmware Hub Interface....................................................................... 10 1.1.2. Address/Address-Multiplexed Interface ...................................................... 10 Nonvolatile Flash Memory Core .................................................................................... 10 Pin Descriptions............................................................................................................. 14 Read 17 Write 17 Output Disable............................................................................................................... 17 Reset 17 Operational Effects of Hardware Write-Protect Pins TBL# and WP# ........................... 18
1.2. 2. 3. 2.1. 3.1. 3.2. 3.3. 3.4. 3.5. 4.
Pinout Configurations ................................................................................................................. 13 Interface Operation Description ................................................................................................. 17
Functional Descriptions.............................................................................................................. 19 4.1. Read Array Command................................................................................................... 21 4.2. Read Identifier Codes Command .................................................................................. 21 4.3. Read Status Register Command................................................................................... 21 4.4. Clear Status Register Command................................................................................... 21 4.5. Block Erase Command ................................................................................................. 22 4.6. Program Command....................................................................................................... 22 4.7. Block Erase Suspend Command .................................................................................. 23 4.8. Program Suspend Comand........................................................................................... 23 4.9. Register Based Locking, General-Purpose Input, and Random Number Generator Registers 23 4.9.1. T_BLOCK_LK and T_MINUSxx_LK -- Block-Locking Registers ............... 25 4.9.2. General-Purpose Input Register ................................................................. 26 4.9.2.1. GPI_REG -- General-Purpose Input Register ............................... 26 4.9.3. Random Number Generator Registers ....................................................... 27 4.9.3.1. RNG Hardware Status Register ..................................................... 27 4.9.3.2. RNG Data Status Register ............................................................. 27 4.9.3.3. RNG Data Register......................................................................... 28 4.10. Using the Random Number Generator ......................................................................... 28 4.11. Detecting and Initializing the RNG Device..................................................................... 28 4.11.1. Detecting the RNG Device .......................................................................... 28 4.11.2. Initializing the RNG Device.......................................................................... 29 4.11.3. Selecting Appropriate FWH IDs and Densities ........................................... 29 4.11.4. Mapping FWH Devices onto Memory Map ................................................. 30 4.11.5. Paging FWH Devices for Greater Than 4 MB of FWH Memory ................. 30 4.11.6. Programming Multiple FWH Devices .......................................................... 30 4.12. CUI Automation Flowcharts........................................................................................... 31
5.
Electrical Specifications ............................................................................................................. 33 5.1. Absolute Maximum Ratings........................................................................................... 33
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5.2.
5.3. 5.4.
5.5. 6. 6.1. 6.2.
Operating Conditions .....................................................................................................33 5.2.1. Interface DC Input/Output Specifications ....................................................34 5.2.2. Interface AC Input/Output Specifications.....................................................36 5.2.3. Intel FWH Interface AC Timing Specifications ............................................37 5.2.3.1. Clock Specification..........................................................................37 5.2.3.2. Signal Timing Parameters...............................................................38 Block Programming Times ............................................................................................40 Intel Firmware Hub Interface..........................................................................................40 5.4.1. Intel FWH Interface Cycles..........................................................................40 5.4.1.1. Read Cycle Sequence.....................................................................40 5.4.1.2. Single-Byte Read Waveforms.........................................................42 5.4.1.3. Write Cycle Sequence.....................................................................42 5.4.1.4. Write Waveforms ............................................................................43 5.4.1.5. Response To Invalid Fields.............................................................43 5.4.1.6. Abort Operations .............................................................................44 5.4.1.7. Intel FWH Cycle Timing Information ...............................................44 RNG Parameters ...........................................................................................................45 Programming ("A/A Mux") Mode Operation ...................................................................47 Bus Operation ................................................................................................................47 6.2.1. Output Disable/Enable.................................................................................47 6.2.2. Row/Column Addresses ..............................................................................47 6.2.3. Read Operation ...........................................................................................47 6.2.4. Read Identifier Codes Operation .................................................................48 6.2.5. Write Operation ...........................................................................................48 Command Definitions ....................................................................................................48 Electrical Characteristics in A/A Mux Mode ...................................................................48 6.4.1. Reset Operations.........................................................................................49 6.4.2. AC Waveforms for Reset Operations ..........................................................49 (1,3) 6.4.3. A/A Mux Read-Only Operations .............................................................49 (1,2) 6.4.4. A/A Mux Write Operations .....................................................................51
PROM Programming Specifications ...........................................................................................47
6.3. 6.4.
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Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Simplified Block Diagram ..................................................................................... 8 Device Memory Map with Intel FWH Hardware Lock Architecture .................... 11 Intel FWH Boot-Configuration System Memory Map......................................... 11 32-Lead PLCC Intel Firmware Hub Pinout......................................................... 13 40-Lead TSOP Intel Firmware Hub Pinout ........................................................ 13 Automated Block Erase Flowchart..................................................................... 31 Clock Waveform ................................................................................................ 37 Output Timing Parameters................................................................................. 38 Input Timing Parameters ................................................................................... 39 FWH Single-Byte Read Waveforms .................................................................. 42 Write Waveforms ............................................................................................... 43 Intel FWH Output Timing Parameters ............................................................... 45 Intel FWH Input Timing Parameters .................................................................. 46 A/A Mux Read Timing Diagram ......................................................................... 50 A/A Mux Write Timing Diagram ......................................................................... 52
Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Pin Descriptions ................................................................................................. 14 Command Definitions......................................................................................... 19 Status Register Definition .................................................................................. 20 Identifier Codes .................................................................................................. 21 Intel Firmware Hub Register Configuration Map................................................ 24 Register-Based Locking Value Definitions......................................................... 25 Temperature and VCC....................................................................................... 33 Intel FWH Interface DC Input/Output Specifications.......................................... 34 Power Supply Specifications -- All Interfaces ................................................... 35 Intel FWH Interface AC Input/Output Specifications.......................................... 36 Clock Specification............................................................................................. 37 Signal Timing Parameters.................................................................................. 38 Interface Measurement Condition Parameters .................................................. 39 AC Waveform for Reset Operation.................................................................... 39 Programming Times .......................................................................................... 40 FWH Read Cycle ............................................................................................... 41 FWH Write Cycle ............................................................................................... 42 Signal Timing Parameters.................................................................................. 44 RNG Timing Characteristics .............................................................................. 45 RNG Statistical Characteristics.......................................................................... 45 Bus Operations .................................................................................................. 48
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Revision History
Rev. -001 -002 * Initial Release * Added Chapter 6 * Updated programmer vendor/service provider information. -003 * Changed VIH min. spec to reflect actual value. * Updated programmer vendor/service provider information. * Clarification of part numbering. * Spec now includes all known issues from all densities/lithographies. * Included FWH memory cycle and RNG information. -004 * Removed All references to multi-byte read cycles * Added DC Characteristics for A/A Mux mode November 2000 May 2000 Draft/Changes Date April 1999 May 1999
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Intel 82802AB/AC Firmware Hub
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Intel(R) 82802AB/AC Firmware Hub (FWH)
Product Features
Intel platform compatability
Enables security-enhanced platform infrastructure; facilitates option to remove ISA. Firmware hub hardware interface mode 5-Signal communication interface supporting byte-at-a-time reads and writes Register-based read and write protection for each code/data storage block Hardware write protect pins for the top boot block and the remaining code/data storage blocks 5 Additional GPIs for platform design flexibility Contains a hardware Random Number Generator (RNG) for enhancing platform security Integrated Command User Interface (CUI) for requesting access to locking, programming, and erasing options. The CUI also handles requests for data residing in status, ID, and block-lock registers. Operates with 33-MHz PCI clock and 3.3 V I/O. Industry-standard packages (40L TSOP or 32L PLCC)
Two configurable interfaces

Firmware hub interface for platform operation Address/Address-Multiplexed (A/A Mux) interface for programming during manufacturing 4 or 8 Mbits of flash memory for platform code/data nonvolatile storage Symmetrically blocked, 64-KB memory sections Available in 8-Mbit (Intel(R) 82802AC) and 4Mbit (Intel(R) 82802AB) densities Automated byte program and block erase via an integrated Write State Machine (WSM) Address/Address-Multiplexed (A/A Mux) interface/mode 11-Pin multiplexed address and 8-pin data I/O interface Supports fast on-board or out-of-system programming for manufacturing Case temprature operating range Power supply specifications Vcc: 3.3 V 0.3 V Vpp: 3.3 V and 12 V for fast programming, (80 hours maximum)
The Intel(R) 82802 (FWH) firmware hub may contain design defects or errors known as errata that may cause the products to deviate from published specifications. Current characterized errata are available upon request.
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Figure 1.
Simplified Block Diagram
Processor
Memory Controller SMBus
Memory ISA Bridge (optional) PCI Bus PCI Slot
SMBus Device(s) AC'97 Codec(s) (optional) IDE (4 drives)
AC'97 IDE USB GPIO
I/O Controller
PCI Agent LPC Interface
Super I/O 82802 Keyboard, Mouse, FD, PP, SP, IR
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1.
Architectural Overview
The Intel(R) 82802 Firmware Hub (FWH) discrete component is compatible with several Intel chipset platforms and a variety of applications. The device operates under the LPC/FWH interface/protocol. The hardware features of this device include a Random Number Generator (RNG), five General-Purpose Inputs (GPIs), register-based block locking, and hardware-based locking. This combination of logic features and non-volatile memory enables better protection for the storage and update of platform code and data, adds platform flexibility through additional GPIs, and allows for quicker introduction of new security/manageability features into current and future platforms. The platform RNG, accessed through the Intel(R) Security Driver and third-party software, enables security features for the PC platform. See the product features listed previously for a list of more key features that the Intel FWH provides.
1.1.
Interface Overview
This device is equipped with two hardware interfaces. The state of the device's "IC" (InterfaceConfiguration) pin determines which interface is in use. The interface mode must be selected prior topower-up or before return from reset (RST# or INIT# low-to-high transition). The Intel FWH interface isdesigned to work with the Intel family of I/O Controller Hubs (ICH) during platform operation. The A/A Mux interface is designed as a programming interface for OEMs, for use during motherboard manufacturing or component pre-programming. The A/A Mux interface is not intended for use during regular personal computer operation. Such a configuration would cause the expected (Intel FWH) interface to be disabled, and the system boot sequence would fail upon power-up. An internal Command User Interface (CUI) serves as the internal control center for the nonvolatilememory core in either of the two device interfaces (Intel FWH or A/A Mux). A single valid commandsequence written to the CUI initiates an automated sequence of internal events to complete various tasks. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program operations. Driving RST# or INIT# low resets the device, which resets the block-lock registers to their default (write-locked) condition and clears the status register. A reset time (tPHQV A/A Mux) is required from RST# or INIT# switching high until outputs are valid. Likewise, the device has a wake time (tPHRH A/A Mux) from RST# or INIT# high until writes to the CUI are recognized. A reset latency will occur if a reset procedure is performed during a programming or erase operation. Resetting the component will put the component back into read-array mode. Note: There is no chip enable (like CE#) in either interface. Stand-by current control in the Inel FWH interface is enabled automatically, if the Intel FWH4 is high and the device is not working to complete a requested activity.
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1.1.1.
Intel Firmware Hub Interface
The Intel Firmware Hub (Intel FWH) interface consists primarily of a 5-signal communication interface used to control the operation of the device in a system environment. The buffers for this interface were designed to be PCI compliant. To ensure the effective delivery of security and manageability features, the Intel FWH interface is the only way access the full feature set of the device. The Intel FWH interface is equipped to operate at 33 MHz, synchronous with the PCI bus.
1.1.2.
Address/Address-Multiplexed Interface
The A/A Mux refers to the multiplexed row and column addresses in this interface. This approach is required so that the device can be tested and programmed quickly with automated test equipment (ATE) or off-board PROM programmers in the OEM's manufacturing flow. This interface also allows the device to have an efficient programming interface with potentially large future densities, while still fitting into a 32-pin package. Only basic reads, programming, and erasure of the nonvolatile memory blocks can be performed through the A/A Mux interface. In this mode, the Intel FWH features, security features, and registers are unavailable. A row/column (R/C#) pin determines which set of addresses (rows or columns) is latched. See the A/A Mux pin description table for more information.
1.2.
Nonvolatile Flash Memory Core
The primary feature of the Intel FWH component is a nonvolatile memory core based on Intel(R) Flash Technology. This high-performance memory array is arranged in eight (4-Mbit device) or sixteen (8Mbit device) 64-KB blocks. Intel(R) Flash Technology enables fast factory programming and low-power designs. Specifically designed for 3-V systems, this component supports read operations at 3.3 V VCC and block erase and program operations at 3.3 V and 12 V VPP. The 12 V VPP option yields the fastest program performance, which will increase factory throughput, but is not recommended for standard in-system FWH operation in the platform, due to an 80-hr limit for 12 V on the VPP pin over the lifetime of the device, whether or not programming is taking place. With the 3.3-V VPP option (recommended for in-system operation), VCC and VPP may be tied together for a simple, low-power 3-V design. In addition to the voltage flexibility, the dedicated VPP pin provides complete data protection when VPP VPPLK. Internal VPP detection circuitry automatically configures the device for block erase and program operations. While current for 12-V programming will be drawn from VPP, 3.3-V programming solutions should design their board such that VPP draws from the same supply as VCC, and should assume that full programming current may be drawn from either pin.
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Figure 2.
Device Memory Map with Intel FWH Hardware Lock Architecture
0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000
64-Kbyte Block 15 64-Kbyte Block 14 64-Kbyte Block 13 64-Kbyte Block 12 64-Kbyte Block 11 64-Kbyte Block 10 64-Kbyte Block 9 64-Kbyte Block 8 64-Kbyte Block 7 64-Kbyte Block 6 64-Kbyte Block 5 64-Kbyte Block 4 64-Kbyte Block 3 64-Kbyte Block 2 64-Kbyte Block 1 64-Kbyte Block 0
} TBL# (8 Mb)
WP# (8 Mb) Blocks 0-14 }TBL# (4 Mb)
WP# (4 Mb)
mem_map_lock
Figure 3.
Intel FWH Boot-Configuration System Memory Map
System Memory (Top 4 MB) FFFFFFFFh FWH 4 Mbit Block 7 FWH 8 Mbit Block 15
FFF80000h Block0
FFF00000h
Block 0
Range for other FWH devices FFC00000h
Sys_memmap_boot
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2.
Figure 4.
Pinout Configurations
32-Lead PLCC Intel Firmware Hub Pinout
A/A Mux A8 A9 RST# VPP VPP VCC R/C# VCC CLK A10 FGPI4 A/A Mux
FGPI2 FGPI3 RST#
4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 FGPI1 FGPI0 WP# TBL# ID3 ID2 ID1 ID0 FWH0 5 6 7 8 9 10 11 12 13 14
3
2
1
32
31
30 29 28 27 IC (VIL) GNDa VCCa GND VCC INIT# FWH4 RFU RFU IC(VIH) GNDa VCCa GND VCC OE# WE# RY/BY# DQ7
IntelFirmware Hub (IntelFWH) 32-Lead PLCC 0.450" x 0.550" Top View
26 25 24 23 22 21
15
16
17
18
19
20
FWH1 FWH2 GND FWH3 RFU A/A Mux DQ1 DQ2 GND DQ3 DQ4
RFU DQ5
RFU DQ6 A/A Mux
Figure 5.
40-Lead TSOP Intel Firmware Hub Pinout
A/A Mux NC IC (VIH) NC NC NC NC A10 NC R/C# VCC VPP RST# NC NC A9 A8 A7 A6 A5 A4 A/A Mux
NC IC (VIL) NC NC NC NC FGPI4 NC CLK VCC VPP RST# NC NC FGPI3 FGPI2 FGPI1 FGPI0 WP# TBL#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Firmware Hub (FWH) 40-LEAD TSOP 10mm x 20mm TOP VIEW
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
GNDa VCCa FWH4 INIT# RFU RFU RFU RFU RFU VCC GND GND FWH3 FWH2 FWH1 FWH0 ID0 ID1 ID2 ID3
GNDa VCCa WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC GND GND DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
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2.1.
Pin Descriptions
The pin descriptions table details the usage of each device pin. Most pins have dual functionality, with functions in both the Intel Firmware Hub and A/A Mux interfaces. The A/A Mux functionality for pins is shown bold italic in the description box for that pin. All pins are designed to be compliant with VCC + 0.3 V max. unless otherwise noted.
Table 1.
Pin Descriptions
Symbol Type Interface Intel FWH IC I X A/A Mux X Interface Configuration Pin. This pin determines which interface is used to communicate with the device. When it is held low, the Intel FWH interface is enabled. When it is held High, the A/A Mux interface is enabled. This pin must be set at power-up or before return from reset, and must not be changed during device operation. This pin is pulled down with an internal resistor of between 20 and 100 k. When the IC is High (A/A Mux mode), this pin will exhibit a leakage current of approximately 200 A. This pin may be floated, which will select the Intel FWH mode. Interface Reset. Valid for both A/A Mux and Intel FWH interface operation. When driven low, RST# inhibits write operations to provide data protection during power transitions, resets internal automation, and tri-states pins FWH[3:0] (in Intel FWH interface mode). RST#-high enables normal operation. When exiting from reset, the device defaults to read array mode. Processor Reset. This is a second reset pin for in-system use. This pin is internally combined with the RST# pin. If this pin or RST# is driven low, identical operation is exhibited. This signal is designed to be connected to the chipset INIT signal (Max. voltage depends on the processor. Do not use 3.3 V). A/A Mux = OE# CLK I X 33-MHz Clock for Intel FWH Interface. This input is the same as that for the PCI clock and adheres to the PCI specification. A/A Mux = R/C# FWH[3:0] I/O X Intel FWH I/Os. I/O communication A/A Mux = DQ[3:0] FWH4 I X Intel FWH Input. Input communication A/A Mux = WE# Name and Function
RST#
I
X
X
INIT#
I
X
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Symbol
Type
Interface Intel FWH A/A Mux
Name and Function
ID[3:0]
I
X
Identification Inputs. These four pins are part of the mechanism that allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component. The boot device must have ID[3:0] = 0000, and it is recommended that all subsequent devices use sequential up-count strapping (0001, 0010,0011,...). These pins are pulled down with internal resistors, with values between 20 and 100 k, when in the Intel FWH mode. Any ID pins pulled high will exhibit a leakage current of approximately 200 A. Any pins intended to be low may be left to float. In a single Intel FWH system, all may be left floating. A/A Mux = A[3:0] Intel FWH General Purpose Inputs. These individual inputs can be used for additional board flexibility. The state of these pins can be read immediately at boot, through Intel FWH registers. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and they should remain at the same level until the end of the read cycle. They may only be used for 3.3-V signals. Unused FGPI pins must not be floated. A/A Mux = A[10:6] Top Block Lock. When low, it prevents programming or block erase to the highest addressable block (7 in a 4-Mbit, 15 in an 8-Mbit component), regardless of the state of the lock register. TBL#-high disables hardware write protection for the top block, though registerbased protection still applies. The status of TBL# does not affect the status of block-locking registers. A/A Mux = A4 Write Protect. When low, prevents programming or block erase to all but the highest addressable block (0-6 in a 4-Mbit, 0-14 in an 8Mbit component), regardless of the state of the corresponding lock registers. WP#-high disables hardware write protection for these blocks, though register-based protection still applies. The status of TBL# does not affect the status of block-locking registers. A/A Mux = A5 Low-Order Address Inputs. Inputs for low-order addresses during read and write operations. Addresses are internally latched during a write cycle. For the A/A Mux interface, these addresses are latched by R/C# and share the same pins as the high-order address inputs. Data Input/Outputs. These pins receive data and commands during CUI write cycles and transmit data during memory array, status register, and identifier code read cycles. Data pins float to high impedance when outputs are disabled. Data is internally latched during a write cycle. Output Enable. Gates the device's outputs during a read cycle Row-Column Address Select. For the A/A Mux interface, this pin determines whether the address pins are pointing to the row addresses (A[0:10]) or the column addresses (A[11:19]). Write Enable. Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse.
FGPI[4:0]
I
X
TBL#
I
X
WP#
I
X
A[0:10]
I
X
DQ[0:7]
I/O
X
OE# R/C#
I I
X X
WE#
I
X
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Symbol
Type
Interface Intel FWH A/A Mux
Name and Function
VPP
PWR
X
X
Block Erase/Program Power Supply. For erasing array blocks or programming data. VPP = 3.3 V or 12 V VPP. With VPP VPPLK, memory contents cannot be altered. Attempting a block erase or program with an invalid VPP (see DC Characteristics) will produce spurious results and should not be attempted. VPP may only be held at 12 V for 80 hours over the lifetime of the device. Device Power Supply. Internal detection automatically configures the device for optimized read performance. Do not float any power pins. With VCC VLKO, all attempts to write to flash memory are inhibited. Device operations at invalid VCC voltages (see DC Characteristics) produce spurious results and should not be attempted. Ground. Do not float any ground pins. Analog Power Supply. This supply should share the same system supply as VCC. Analog Ground. Should be tied to same plane as GND. Reserved For Future Use. These pins are reserved for future generations of this product. They may be left disconnected or driven. If they are driven, the voltage levels should satisfy VIH and VIL requirements. A/A Mux = DQ[7:4]
VCC
PWR
X
X
GND VCCa GNDa
PWR PWR PWR
X X X
X X X
RFU
X
NC
X
X
No Connect. Pin may be driven or floated. If it is driven, the voltage levels should satisfy VIH and VIL. No connects appear only on the 40ld TSOP package. Ready/Busy. Valid only in A/A Mux Mode. This output pin is a reflection of bit 7 in the Status Register. This pin is used to determine block erase or program completion.
Ry/By#
0
X
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3.
3.1.
Interface Operation Description
Read
Memory information, identifier codes, GPI registers or the status register can be read, regardless of the VPP voltage. Commands using the read mode include: reading memory from the array, reading the identifier codes, reading the status register, reading the lock bit registers, reading the random number generator, reading the GPI registers, and reading the RNG status register. Upon initial device power-up or after exit from reset, the device automatically resets to read array mode.
3.2.
Write
Writes to the memory array's CUI are initiating by issuing a write through the Intel FWH interface. (See the following information on timing and Intel FWH cycle write protocol specifics.) The CUI does not occupy a single, specific memory location--any valid address may be given. However, certain commands, such as block erase, require the address be within the range of the desired address block.
3.3.
Output Disable
When the Intel FWH is not selected through a FWH read or write cycle, the Intel FWH interface outputs (FWH[3:0]) are disabled and is placed in a high-impedance state.
3.4.
Reset
RST# or INIT# at VIL initiates a device reset. In the read mode, RST# or INIT# low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. RST# or INIT# must be held low for time tPLPH (A/A Mux and FWH operation). The Intel FWH resets to read array mode upon return from reset, and all blocks are set to default (locked) status (see 4.9.1), regardless of their locked state prior to reset. During block erase or program, driving RST# or INIT# low will abort the operation underway, in addition to causing a reset latency. Memory contents being altered are no longer valid, since the data may be partially erased or programmed. It is important to assert RST# or INIT# during system reset. When the system comes out of reset, it will expect to read from the memory array of the device. If a system reset occurs with no FWH reset--this is hardware dependent--it is possible that proper processor initialization will not occur. (The Intel FWH memory may be providing status information instead of memory array data.)
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3.5.
Operational Effects of Hardware Write-Protect Pins TBL# and WP#
The TBL# and WP# pins on the Intel FWH provide hardware write protect capabilities. The Top Block Lock (TBL#) pin, when held low (active), prevents program or block erase operations in the top-most block of the device where critical code can be stored. When TBL# is high, hardware write protection of the top block is disabled. The Write Protect (WP#) pin has a function similar to TBL#, but affects all remaining blocks. WP# operates independently from TBL# and does not affect the lock status of the top block. The TBL# and WP# pins must be set to the desired protection state prior to starting a program or erase operation, since they are sampled at the beginning of the operation. Changing the state of TBL# or WP# during a program or erase operation may cause unpredictable results. If the state of TBL# or WP# changes during a program suspend or erase suspend state, the changes to the device's locking status do not take place immediately. The suspended operation may be resumed to successfully complete the program or erase operation. The new lock status will take place after the program or erase operation completes. These pins function in combination with the register-based block locking described in Section 4.9. When active, these pins write-protect the appropriate block(s), regardless of the associated block-locking registers. (For example, when TBL# is active, writing to the top block is prevented, regardless of the state of the write-lock bit for the top block's locking register. In such a case, clearing the write-protect bit in the register will have no functional effect, even though the register may indicate that the block is no longer locked. The register may still be set to read-lock the block, if desired.) See Section 4.9 for further information.
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4.
Functional Descriptions
When the VPP voltage VPPLK, read operations from the status register, identifier codes or memory are enabled, but programming and erase functions are disabled. Placing VPPH1/2 on VPP enables successful block erase and program operations.
Table 2.
Command Definitions
Command Bus Cycles Required Notes First Bus Cycle Oper. Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Program 1 2 2 1 2 2 3 3,4 2 Write Write Write Write Write Write Addr.(1) X X X X BA WA Data(2) FFh 90h 70h 50h 20h 40h or 10h B0h D0h Write Write BA WA D0h WD Read Read IA X ID SRD Second Bus Cycle Oper. Addr.(1) Data(2)
Block Erase and Program Suspend Block Erase and Program Resume
1 1
3 3
Write Write
X X
Note: 1. Key: X = Any valid address within the device IA = Identifier Code Address BA = Address within the block being erased WA = Address of memory location to be written SRD = Data read from status register. WD = Data to be written at location WA ID = Data read from identifier codes Following the Read Identifier Codes command, read operations access manufacturer and device. See Table 4 for the read identifier code data. The block must not be write locked when attempting block erase or program operations. Attempts to issue a block erase or program to a write-locked block will fail. Either 40h or 10h are recognized by the WSM as the program setup.
2. 3. 4. Note:
Commands other than those shown previously are reserved by Intel for future device implementations and should not be used.
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Table 3.
Status Register Definition
7 WSMS 6 ESS 5 ES 4 PS 3 VPPS 2 PSS 1 DPS 0 R
Bit 7
Description Write State Machine Status (SR.7). Check SR.7 to determine block erase or program completion. SR.6-0 are invalid while SR.7 = 0. 1 = Ready 0 = Busy
6
Erase Suspend Status (SR.6). 1 = Block erase suspended 0 = Block erase in progress/completed
5
Erase Status (SR.5). If both SR.5 and SR.4 are 1s after a block erase attempt, an improper command sequence was entered. 1 = Error in block erasure 0 = Successful block erase
4
Program Status (SR.4). 1 = Error in program 0 = Successful program
3
VPP Status (SR.3). SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after a block erase or program operation. SR.3 is not guaranteed to reports accurate feedback only when VPP VPPH1/2. 1 = VPP low detect, operation abort 0 = VPP OK
2
Program Suspend Status (SR.2). 1 = Program suspended 0 = Program in progress/completed
1
Device Protect Status (SR.1). SR.1 does not provide a continuous indication of write-lock bit, TBL# pin or WP# pin values. The WSM interrogates the write-lock bit, TBL# pin or WP# pin only after a block erase or program operation. Depending on the attempted operation, it informs the system whether or not the selected block is locked. 1 = Write-lock bit, TBL# pin, or WP# pin Detected, operation abort 0 = Unlock
0
Reserved for future enhancements (SR.0). SR.0 is reserved for future use and should be masked out when polling the status register.
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4.1.
Read Array Command
Upon initial device power-up and after exit from reset, the device defaults to the read array mode. This operation can also be initiated by writing the Read Array command. The device remains available for array reads until another command is written. Once the internal write state machine (WSM) has started a block erase or program, the device will not recognize the Read Array command until the operation is completed, unless the operation is suspended via an Erase Suspend or Program Suspend command. The Read Array command functions independently of the VPP voltage.
4.2.
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. Following the write of the command, the device will read back the (manufacturer and device) ID data from the addresses shown in the following table. To terminate the read identifier code operation, write another valid command to the Intel FWH. The Read Identifier Codes command functions independently of the VPP voltage.
Table 4.
Identifier Codes
Code Manufacturer code Device code Device code 4 Mbit 8 Mbit Address 000000 000001 000001 Data 89 AD AC
4.3.
Read Status Register Command
The status register may be read to determine when a block erase or program completes, and whether the operation completed successfully. The status register may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations will return data from the status register until another valid command is written. The Read Status Register command functions independently of the VPP voltage.
4.4.
Clear Status Register Command
Error flags in the status register can only be set to 1s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various conditions that may cause failure. The Clear Status Register command functions independently of the applied VPP voltage.
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4.5.
Block Erase Command
The erase command operates on one block at a time. This command requires an (arbitrary) address within the block to be erased. Recall that erasure changes all block data to FFh. Block preconditioning, erase, and erase verify are handled internally by the WSM, which is transparent to the system. After issuing the erase command, the device automatically outputs status register data when read. When the block erase completes, the status register may be checked. If the FWH detects a block erase error, the status register should be cleared before system software attempts corrective actions. After a block erase, the CUI remains in read status register mode until a new command is issued. Successful block erasure requires that the corresponding block's write-lock-bit is cleared, and the corresponding write-protect pin (TBL# or WP#) is inactive. If a block erase is attempted when the block is locked, the block erase will fail, with the reason for failure in the status register. Successful block erase only occurs when VPP = VPPH1 or VPPH2. If the erase operation is attempted at VPP VPPH1 or VPPH2, erratic results may occur.
4.6.
Program Command
Program command operates on one byte at a time. This command specifies the address and data to be programmed. After the CUI receives the command, the WSM takes over, controlling the program and verify algorithms internally. After the program command is written, the device automatically outputs the status register data when read. When programming is complete, the status register may be checked. If a program error is detected, the status register should be cleared before corrective action is taken by the software. The internal WSM verification error checking only detects 1s that does not successfully program to 0s. The CUI remains in read status register mode until it receives another command. Reliable programming only occurs when VPP = VPPH1 or VPPH2. If programming is attempted at VPP VPPH1 or VPPH2, erratic results may occur. Successful program operation also requires that the corresponding block's write-lock bit be cleared and that the corresponding write-protect pin (TBL# or WP#) be inactive. If program operation is attempted when the block is locked, the operation will fail.
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4.7.
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling the status register can help determine when the block erase operation was suspended. After a successful suspend, a Read Array command may be written to read data from a block other than the suspended block. A Program command sequence may also be issued during erase suspend to program data in blocks other that the block currently in the erase suspend mode. The other valid commands while block erase is suspended include Read Status Register and Block Erase Resume. After a Block Erase Resume command is written, the WSM will continue the block erase process. VPP must remain at VPPH1/2 (the same VPP level initially used for the block erase) while block erase is suspended. RST# or INIT# must also remain at VIH. Block erase cannot resume until program operations initiated during block erase suspend have completed.
4.8.
Program Suspend Comand
The Program Suspend command allows program interruption to read data in other memory locations. Once the program process starts, writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Program Suspend command is written. Polling status register bits will help determine when the program operation was suspended. After a successful suspend, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while program is suspended are Read Status Register and Program Resume. After Program Resume command is written, the WSM will continue the programming process. VPP must remain at VPPH1/2 (the same VPP level used for program) while in program suspend mode. RST# or INIT# must also remain at VIH.
4.9.
Register Based Locking, General-Purpose Input, and Random Number Generator Registers
A series of registers are available in the Intel FWH to provide software read- and write-locking and GPI feedback. Also available are the set of control registers for controlling and gathering random numbers. These registers are accessible through standard addressable memory space (see the following table). It is recommended that the GPI pins be in the desired state before FWH4 is brought low for the beginning of the next bus cycle, and remain in that state until the end of the read.
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Table 5.
Intel Firmware Hub Register Configuration Map
Memory Address FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h FFB70002h FFB60002h FFB50002h FFB40002h FFB30002h FFB20002h FFB10002h FFB00002h FFBC0100h FFBC015Fh FFBC0160h FFBC0161h Mnemonic T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK T_MINUS08_LK T_MINUS09_LK T_MINUS10_LK T_MINUS11_LK T_MINUS12_LK T_MINUS13_LK T_MINUS14_LK T_MINUS15_LK FGPI_REG Register Name Top Block Lock Register (4-8-Mbit FWH) Top Block [-1] Lock Register (4-8-Mbit FWH) Top Block [-2] Lock Register (4-8-Mbit FWH) Top Block [-3] Lock Register (4-8-Mbit FWH) Top Block [-4] Lock Register (4-8-Mbit FWH) Top Block [-5] Lock Register (4-8-Mbit FWH) Top Block [-6] Lock Register (4-8-Mbit FWH) Top Block [-7] Lock Register (4-8-Mbit FWH) Top Block [-8] Lock Register (8-Mbit FWH) Top Block [-9] Lock Register (8-Mbit FWH) Top Block [-10] Lock Register (8-Mbit FWH) Top Block [-11] Lock Register (8-Mbit FWH) Top Block [-12] Lock Register (8-Mbit FWH) Top Block [-13] Lock Register (8-Mbit FWH) Top Block [-14] Lock Register (8-Mbit FWH) Top Block [-15] Lock Register (8-Mbit FWH) FWH General-Purpose Input Register RNG Hardware Status Register RNG Data Status Register RNG Data Register Default 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h N/A 40h* 0 N/A Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W RO RO
* Assumes RNG is present and not disabled.
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4.9.1.
T_BLOCK_LK and T_MINUSxx_LK -- Block-Locking Registers
Memory Address: Default Value: Access: Size:
Bit 7:3 Reserved Read-Lock 2 1 = Prevents read operations in the block where set. 0 = Normal operation for reads in the block where clear. This is the default state. Lock-Down 1 = Prevents further set or clear operations to the Write Lock and Read Lock bits. Lock-Down only can be set, but not cleared. The block will remain locked-down until reset (with RST# or INIT#), or until the device is power-cycled. 0 = Normal operation for Write Lock and Read Lock bit altering in the block where clear. This is the default state. Write-Lock 0 1 = Prevents program or erase operations in the block where set. This is the default state. 0 = Normal operation for programming and erase in the block where clear.
FFBx0002h (x = F-0h) 01h R/W 8 bits (each)
Function
1
Table 6.
Register-Based Locking Value Definitions
Data 00h 01h 02h 03h 04h 05h 06h 07h Reserved Data 7:3 00000 00000 00000 00000 00000 00000 00000 00000 Read Lock, Data 2 0 0 0 0 1 1 1 1 Lock-Down, Data 1 0 0 1 1 0 0 1 1 Write Lock, Data 0 0 1 0 1 0 1 0 1 Resulting block state (1). Full access Write locked. Default state at powerup Locked open (full access locked down). Write-locked down. Read locked. Read and write locked. Read-locked down. Read- and write-locked down.
Note:
The write-lock bit must be set to the desired protection state prior to starting a program or erase operation, since it is sampled at the beginning of the operation. Changing the state of the write-lock bit during a program or erase operation may cause unpredictable results. If the state of the write-lock bit changes during a program suspend or erase suspend state, changes in the block's locking status do not occur immediately. The suspended operation may be resumed successfully. The new lock status will take place after the program or erase operation completes. The individual bit functions are described in the following sections.
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Write Lock
The default write status of all blocks upon power-up is write-locked. Any program or erase operations attempted on a locked block will return an error in the status register (indicating block lock). The status of the locked block can be changed to unlocked by clearing the write-lock bit, provided the lock-down bit also is not set. The current write-lock status of a particular block can be determined by reading the corresponding write-lock bit. The write-lock functions in conjunction with the hardware write-lock pins, TBL# and WP#. When active, these pins take precedence over the register locking function and writelock the top block or remaining blocks, respectively. Reading this register will not read the state of the TBL# or WP# pin.
Read Lock
The default read status of all blocks upon power-up is read-unlocked. When a block's read-lock bit is set, data cannot be read from that block. An attempted read from a read-locked block will result in the data 00h. (Note that failure is not reflected in the status register.) The read-lock status can be unlocked by clearing the read-lock bit, provided the lock-down bit has not been set. The current read-lock status of a particular block can be determined by reading the corresponding read-lock bit.
Lock-Down
In the Intel FWH interface mode, the default lock-down status of all blocks upon power-up is not-lockeddown. The lock-down bit for any block may be set, but only once, because future attempts to change that block-locking register will be ignored. The lock-down bit is cleared only upon a device reset with RST# or INIT#. The current lock-down status of a particular block can be determined by reading the corresponding lock-down bit. Once a block's lock-down bit is set, the read- and write-lock bits for that block can no longer be modified, and the block is locked-down in its current state of read and write accessibility.
4.9.2.
General-Purpose Input Register
This register reads the status of the FGPI [4:0] pins on the Intel FWH. Since this is a pass-through register, there is no default value, only the state of the pins at power-up.
4.9.2.1.
GPI_REG -- General-Purpose Input Register
Memory Address: Default Value: Access: Size:
Bit 7:5 4 3 2 1 0 Reserved FGPI[4]. Reads status of general-purpose input pin (PLCC-30/TSOP-7). FGPI[3]. Reads status of general-purpose input pin (PLCC-3/TSOP-15). FGPI[2]. Reads status of general-purpose input pin (PLCC-4/TSOP-16). FGPI[1]. Reads status of general-purpose input pin (PLCC-5/TSOP-17). FGPI[0]. Reads status of general-purpose input pin (PLCC-6/TSOP-18).
FFBC0100h N/A R0 8 bits
Function
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4.9.3.
Random Number Generator Registers
When enabled and active, the Random Number Generator (RNG) is designed to fill an 8-bit register, a bit at a time, with hardware-generated random numbers. When this register is full, a flag bit in the RNG data status register transitions to a 1, indicating that a valid random number is ready to be read. This bit will immediately reset to 0 upon reading the RNG data register. The advantages of random numbers over pseudo-random numbers as well as a brief overview of the simple mathematics of testing RNGs are discussed superficially in the companion document, The Intel(R) Platform RNG Tech Brief, which is available online.
4.9.3.1.
RNG Hardware Status Register
Memory Address: Default Value: Access: Size:
Bit 7 6 Reserved RNG Present--RO. Determines whether or not an RNG is present on this component, or if it has been disabled. 1 = RNG Present 0 = RNG not present 5:1 0 Reserved RNG Enabled--R/W. Determines whether the RNG is generating a random number. 1 = RNG enabled 0 = RNG disabled
FFBC015Fh 40h, for typical component out of reset RO 8 bits
Function
4.9.3.2.
RNG Data Status Register
Memory Address: Default Value: Access: Size:
Bit 7:1 0 Reserved RNG Output Valid. Determines whether the RNG data register contains a valid random number. 1 = RNG data register contians valid random data 0 = RNG data register contents not valid
FFBC0160h 00h RO 8 bits
Function
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4.9.3.3.
RNG Data Register
Memory Address: Default Value: Access: Size:
Bit 7:0
FFBC0161h 40h, for typical component out of reset RO 8 bits
Function
RNG Output: (Should only be used if RNG Data Status Register indicates valid output.)
4.10.
Using the Random Number Generator
The Intel Firmware Hub integrates a Random Number Generator that utilizes thermal noise generated as a result of the inherently random quantum mechanical properties of silicon, in order to modulate a proven hardware RNG design. Internal circuitry is included to enhance the entropy of the output. Since the output of the RNG is non-deterministic, it is an excellent choice for cryptography applications, but it also is a convenient source of random numbers for mathematics, modeling, graphics algorithms, artificial intelligence, entertainment, and many other applications. The fact that it is a component of the platform and may be utilized remotely on a locked-away server makes it an ideal (and much more reliable) source of entropy for applications that, in the past, have relied exclusively on a key press or other environmental input. Several Intel Firmware Hub components may be used in tandem (see the following section) when additional RNG bandwidth is required. When not generating new random bits, the RNG circuitry will enter a low power state.
4.11.
Detecting and Initializing the RNG Device
Before any process attempts to read random data directly from the Intel Firmware Hub RNG device, it should execute a process to verify that a supported RNG device is available for use, enable the device, and verify the correct functionality. This initialization process is described in a following subsection.
4.11.1.
Detecting the RNG Device
The Manufacturer Code and Hardware Status registers are used to determine whether a supported RNG device is available on the system. Step 1: From the system BIOS or using the Read Identifier Codes command, as specified in the Intel(R) 82802AB/82802AC Firmware Hub (FWH) datasheet, verify the Intel(R) 82802 manufacturer code. Step 2: If a valid Intel(R) 82802 FWH is found, then the RNG Present bit (bit 6) of the Hardware Status register should be checked in order to verify that an RNG device is available.
Note:
There is a chance that, even if no RNG device is present, the physical memory locations described above may coincidentally match the values expected for an RNG device. For this reason, before random data is sent to an application, the device should be exercised to verify that it is indeed an RNG. This can be accomplished by enabling the device and running an initial test (e.g., FIPS (Federal Information Processing Standard) 140-1) before use.
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4.11.2.
Initializing the RNG Device
Once the RNG device is detected, it must be enabled and should be tested before use. Step 1: The RNG Enabled bit (bit 0) of the Hardware Status register must be set to enable the RNG device. Step 2: Once the RNG is enabled, an initial read of the RNG Data register should be made to clear any preexisting data from the register. Step 3: A test (e.g., FIPS 140-1) should be run on the RNG Device. This test will ensure that there was no error in detecting the device and that the device is functioning properly.
4.11.3.
Selecting Appropriate FWH IDs and Densities
It is possible, using different ID strapping, to use multiple FWH components in a system. While the FWH protocol supports up to 16 FWH devices, the BIOS support, bus loading or the attaching bridge may limit this number. Note that, regardless of the number of FWH components, the maximum "window" of the FWH array visible at one time is 4 MB (for Intel(R) ICH1) and 8MB for Intel(R) ICH2. The boot device must have an ID (as determined by ID [0:3]) of 0. For clarity, it is advisable that subsequent devices use incremental numbering. The most straightforward method of using multiple FWH components is to use devices of equal density. This is the recommended technique. In special applications, when it is desirable to use multiple FWH components of different densities--if multiple RNGs or more GPIs are required, for instance, without the need for greater array space--IDs must be chosen such that component memory array spaces do not cross the boundaries delimited by the highest-capacity device, as illustrated in the following table. For example, in a design with 8- and 4-Mbit components, the 8-Mbit part must either be first or must be after enough 4-Mbit parts to add up to a multiple of 8 Mbits.
Yes 8 Mbits
No 4 Mbits
Yes 4 Mbits
8 Mbits
4 Mbits
4 Mbits
8 Mbits Biggest is 8 Mbits.
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4.11.4.
Mapping FWH Devices onto Memory Map
There is 4 MB of available memory space devoted to the FWH. Therefore, the Intel ICH has the ability to select which FWH device maps into each region of the system address space. In the existing Intel ICH, the address map is broken up into eight 512-KB segments. The BIOS Select Register in the Intel ICH is a 32-bit register that contains the needed mapping information, thereby determining which FWH receives requests from which portion of the address map. For example, in a system with four 8-Mbit devices, this register would be 00112233h, which is the default power-up state for this register. In a system with eight 4-Mbit devices, the register must be changed to 01234567h.
Note:
The FWH indicated in the most-significant nibble of the register may be shadowed elsewhere in the system memory map. The FWH with ID 0 may not be re-mapped.
4.11.5.
Paging FWH Devices for Greater Than 4 MB of FWH Memory
In certain applications, even a 4-MB window of flash memory is inadequate. It is possible to exceed this amount by using a paging scheme. Individual FWH devices may then be "swapped" in and out of system memory space. This must be implemented at the BIOS level, to permit modification of the Intel ICH BIOS Select Register. A number of paging algorithms may be used successfully with the FWH memory space, using the Intel ICH BIOS Select Register. This register, then, determines which FWH device gets mapped into each 512 KB "slice" of the system memory map. The 0th FWH (ID=0) may not be remapped. Reference the Intel(R) 82801AA (ICH) and Intel(R) 82801AB (ICH0) I/O Controller Hub Datasheet (order number: 290655) for information regarding these components and the BIOS Select Register.
Note:
The paging of FWH devices will also "page" features, potentially affecting the visibility or location of the FGPI register (see Section 4.9.2.1) or of an active/ready RNG. When a paging scheme is used, it is recommended that critical FPGIs be used only on the ID 0 FWH device, which must remain mapped at the top of memory. Ideally, the RNG driver in a system with more than four FWHs should verify the mapping of FWHs in order to keep track of which RNGs are active and which are present in the memory map. There is no convenient way, aside from checking the select register, to determine which IDed FWH is in which location in the memory map.
4.11.6.
Programming Multiple FWH Devices
Special considerations must be taken into account when programming multiple FWH devices in-system. Since there is no ID support in the A/A Mux mode, the recommended means of programming multiple devices is either out-of-system programming with standalone PROM programmers or in-system programming using the FWH mode. In cases where programming time is critical or ATE programming is required, provisions should be made to isolate the component from its neighboring devices during A/A Mux programming, or the other devices should be held in a reset (or otherwise disabled) state until programming of the intended device is complete. Do not switch one component into the A/A Mux mode, thereby leaving the others in the FWH mode.
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4.12.
Figure 6.
CUI Automation Flowcharts
Automated Block Erase Flowchart
Start
Bus Operation Write
Command
Comments
Write 20h, Block Address
Erase Setup
Data = 20h Addr = Within Block to Be Erased Data = D0h Addr = Within Block to Be Erased
Write Write D0h, Block Address Read
Erase Confirm
Read Status Register
Status Register Data
Standby 0 SR.7 =
Check SR.7 1 = WSM Ready 0 = WSM Busy
1 Full Status Check if Desired
Repeat for subsequent block erasures. Full status check can be done after each block erase, or after a sequence of block erasures. Write FFh after the last operation to place device in read array mode.
Block Erase Complete
Full Status Check Procedure
Read Status Register Data (See Above)
Bus Operation Standby
Command
Comments
SR.3 =
1
Check SR.3 1 = VPP Error Detect
Check SR.4,5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error
VPP Range Error
Standby
1 SR.4,5 = 0 1 SR.5 = 0 Block Erase Successful
Command Sequence Error
Standby
Block Erase Error
SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery.
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5.
5.1.
Electrical Specifications
Absolute Maximum Ratings
Case temperature under bias:......................... -10 C to +85 C Storage temperature: ................................... -65 C to +125 C Supply voltage with respect to VSS ..................-0.2 V to 4.1 V Voltage On Any Pin (except VPP):-0.5 V to +VCC + 0.5 V(1,2,5) VPP voltage: ........................................... -0.5 V to +14.0 V(1,2,4) Output short-circuit current: ...................................... 100 mA(3) *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Note: 1. All specified voltages are with respect to GND. The minimum DC voltage on the VPP pin is -0.5 V. During transitions, this level may undershoot to -2.0 V for periods of <20 ns. During transitions, this level may overshoot to VCC + 2.0 V for periods of <20 ns. The maximum DC voltage on VPP may overshoot to +14.0 V for periods of <20 ns. Output shorted for no more than one second. No more than one output is shorted at a time. This note applies only to non-PCI outputs. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours. Do not violate processor or chipset limitations on the INIT# pin.
2. 3. 4. 5.
5.2.
Table 7.
Operating Conditions
Temperature and VCC
Symbol TC VCC Parameter Operating temperature VCC supply voltage (3.3 V 0.3 V) Notes 1 Min. 0 3.0 Max. +85 3.6 Unit C V Test Condition Case temperature
Note: 1. This temperature requirement differs from the normal commercial operating condition of flash memories.
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5.2.1.
Table 8.
Interface DC Input/Output Specifications
Intel FWH Interface DC Input/Output Specifications
Symbol VIH VIH (INIT#) VIL IIL VOH VOL CIN CCLK Lpin Parameter Input high voltage INIT# input high voltage Input low voltage Input leakage current Output high voltage Output low voltage Input pin capacitance CLK pin capacitance Recommended pin inductance 3 0 < Vin < VCC Iout = -500 A Iout = 1500 A 0.9 VCC 0.1 VCC 13 12 20 Conditions Min. 0.5 VCC 1.35 -0.5 Max. VCC +0.5 VCC +0.5 0.3 VCC 10 Units V V V A V V pF pF nH 2 Notes 3 5 3 1,4
Note: 1. 2. 3. 4. 5. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. Refer to PCI spec. Inputs are not "5 volt safe." IIL may be changed on IC and ID pins (up to 200A), if pulled against internal pull-downs. Refer to the pin descriptions (Table 1). Do not violate processor or chipset specifications regarding the INIT# pin voltage.
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Table 9.
Power Supply Specifications -- All Interfaces
Symbol VPPH1 VPPH2 VPPLK VLKO ICCSL1 Parameter VPP voltage VPP voltage VPP lockout voltage VCC lockout voltage VCC stand-by current (FWH interface) Voltage range of all inputs is VIH to VIL, FWH4 = VIH, VCC = 3.6 V, CLK f = 33 MHz No internal operations in progress. ICCSL2 VCC stand-by current (FWH interface) FWH4 = VIL VCC = 3.6 V, CLK f = 33 MHz No internal operations in progress. ICCA VCC active current VCC = VCC Max, CLK f = 33 MHz Any internal operation in progress, IOUT = 0mA IPPR IPPWE VPP read current VPP program or erase current VPP VCC VPP = 3.0-3.6 V VPP = 11.4-12.6 V 200 40 15 A mA mA 2 2 2 67 mA 2,3,5 10 mA 2,3,4 Conditions Min. 3.0 11.4 1.5 1.5 100 Max. 3.6 12.6 Units V V V V A 2,3,4 Notes
Note: 1. 2. 3. 4. All currents are RMS, unless otherwise noted. These currents are valid for all packages. VPP = VCC VIH = 0.9 VCC , VIL = 0.1 VCC per the PCI output VOH and VOL specifications of Table 8. This number is the worst case of IPP + ICC memory core + ICC FWH interface.
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5.2.2.
Table 10.
Interface AC Input/Output Specifications
Intel FWH Interface AC Input/Output Specifications
Symbol Ioh(AC) Parameter Switching current High Condition 0 < VOUT 0.3 VCC 0.3 VCC < VOUT < 0.9 VCC 0.7 VCC < VOUT < VCC (Test point) Iol(AC) Switching current Low VOUT = 0.7 VCC VCC > VOUT 0.6 VCC 0.6 VCC > VOUT > 0.1 VCC 0.18 VCC > VOUT > 0 (Test point) Icl Ich slewr slewf Low clamp current High clamp current Output rise slew rate Output fall slew rate VOUT = 0.18 VCC -3 < VIN -1 VCC +4 > VIN VCC+1 0.2 VCC - 0.6 VCC load 0.6 VCC - 0.2 VCC load -25 + (VIN+1) / 0.015 25 + (VIN-VCC-1) / 0.015 1 1 4 4 16 VCC -17.1 (VCC -VOUT) Equation D 38 VCC mA mA mA V/ns V/ns 1 1 Min. -12 VCC -17.1 (VCC -VOUT) Equation C -32 VCC mA mA mA Max. Units mA mA Notes
Note: 1. PCI specification output load is used.
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5.2.3.
5.2.3.1.
Table 11.
Intel FWH Interface AC Timing Specifications
Clock Specification
Clock Specification
Symbol tcyc thigh tlow Parameter CLK cycle time CLK high time CLK low time CLK slew rate RST# or INIT# slew rate Peak-to-peak Condition Min. 30 11 11 1 50 4 Max. Units ns ns ns V/ns mV/ns 2 Notes 1
Note: 1. PCI components must work with any clock frequency between nominal DC and 33 MHz. Frequencies less than 16 MHz may be guaranteed by design rather than testing. Refer to the PCI specificaiton. Applies only to the rising edge of the signal. See Chapter 4 of the PCI electrical specification. Clock Waveform
2. Figure 7.
T_cyc T_high 0.6 Vcc 0.5 Vcc 0.4 Vcc 0.3 Vcc 0.2 Vcc 0.4 Vcc, p-to-p (minimum) T_low
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5.2.3.2.
Table 12.
Signal Timing Parameters
Signal Timing Parameters
Symbol TCHQV TCHQX TCHQZ TAVCH TDVCH TCHAX TCHDX TVSPL TCSPL TPLQZ PCI Symbol tval ton toff tsu th trst trst-clk trst-off Parameter CLK to data out CLK to active (float to active delay) CLK to inactive (active to float delay) Input setup time Input hold time Reset active time after power stable Reset active time after CLK stable Reset active to output float delay 7 0 1 100 48 Condition Min. 2 2 28 Max. 11 Units ns ns ns ns ns ms s ns 2 Notes 1 2 2 3 3
Note: 1. 2. Minimum and maximum times have different loads. See PCI spec. For purposes of active/float timing measurements, the Hi-Z or Off state is defined as that in which the total current delivered through the component pin is less than or equal to the leakage current specification. This parameter applies to any input type (excluding CLK). Output Timing Parameters
3. Figure 8.
V_th
CLK
V_test T_val
V_tl
FWH[3:0] (Valid Output Data)
FWH[3:0] (Float Output Data)
T_on T_off
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Figure 9.
Input Timing Parameters
V_th
CLK
T_su
V_test
V_tl
T_h
FWH[3:0] (Valid Input Data)
Inputs Valid
V_max
Table 13.
Interface Measurement Condition Parameters
Symbol Vth Vtl Vtest Vmax Input signal edge rate Value 0.6 VCC 0.2 VCC 0.4 VCC 0.4 VCC 1 V/ns 1 Units V Notes 1 1
Note: 1. The input test environment uses 0.1 VCC of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. Vmax specifies the maximum peak-to-peak waveform allowed for measuring the input timing. Production testing may use different voltage values, but must correlate results back to these parameters.
Reset Operations
RST# (P) VIH V
IL P1
Table 14.
AC Waveform for Reset Operation
# P1(1) Symbol tPLPH Parameter RST# or INIT# pulse low time (If RST# or INIT# is tied to VCC, this specification is not applicable.) Min. 100 Max. Unit ns Notes 1
Note: 1. There will be a 20-s reset latency if a reset procedure is performed during a programming or erase operation.
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5.3.
Table 15.
Block Programming Times
Programming Times
3.3 V VPP Parameter Byte program time Block program time Block erase time Notes 2 2 2 Typ.(1) 17 1.1 0.8 Max. 300 4.0 6.0 12 V VPP Typ.(1) 7.0 0.5 0.3 Max. 125 1.5 4.0 Unit s sec sec
Note: 1. 2. Typical values measured at TA = +25C and nominal voltages. Excludes system-level overhead.
5.4.
Intel Firmware Hub Interface
The firmware hub relies on the Intel Firmware Hub interface to communicate with the outside world. This interface consists of four bi-directional signals and one "control" input. The timing and electrical parameters of the FWH interface are similar to those of the LPC interface, to provide compatibility between the interfaces, but differ in cases mentioned earlier in this section (clock pin capacitance), as well as in certain timing parameters. The Intel ICH has been engineered to accommodate both interfaces, which allows the Intel FWH interface signals to be communicated over the same set of pins as LPC. The Intel FWH interface is designed to use an LPC-compatible start cycle, with a reserved cycle type code. This ensures that all LPC devices present on the shared interface will ignore cycles destined for the FWH, without becoming "confused" by the different protocol. This section contains timing and protocol information for the Intel FWH interface. Note that the Intel FWH interface is a licensed interface, so the appropriate license must be obtained from Intel for components supporting the Intel FWH interface (e.g., ASICs, PLDs).
5.4.1.
Intel FWH Interface Cycles
When the Intel FWH interface is active, information is transferred to and from the FWH by a series of "fields," where each field contains 4 bits of data. Many fields are one clock cycle in length but can be of variable length, depending upon the nature of the field. Field sequences and contents are strictly defined for read and write operations. The following tables list the field sequences for read and write cycles. Addresses in this section refer to addresses as seen from the FWH's "point of view," so some calculation will be required to translate these to the actual locations in the memory map (and vice versa).
5.4.1.1.
Read Cycle Sequence
The firmware hub supports single-byte or multibyte reads. The logic waveforms for these cycles are shown in Table 16 and Figure 11
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Table 16.
FWH Read Cycle
Clock Cycle 1 Field Name START Field Contents1 FWH[3:0] 1101 FWH[3:0] Direction IN Comments FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitioning high) should be recognized. The START field contents indicate an FWH memory read cycle. Indicates which FWH device should respond. If the IDSEL (ID select) field matches the value ID[3:0], then that particular device will respond to subsequent commands. These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. On multibyte data transfers, lower-order addresses will be zero, depending on page size. A field of this size indicates how many bytes will be transferred during multibyte operations. The FWH will only support single-byte transfers. In this clock cycle, the master (Intel ICH) has driven the bus to all 1s and then floats the bus, prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The FWH takes control of the bus during this cycle. During the next clock cycle, it will be driving "sync data." The FWH outputs the value 0101, a wait-sync (WSYNC, a.k.a. "short-sync"), for two clock cycles. This value indicates to the master (Intel ICH) that data is not yet available from the part. This number of wait-syncs is a function of the device's access time. During this clock cycle, the FWH will generate a "readysync" (RSYNC) indicating that the least-significant nibble of the least-significant byte will be available during the next clock cycle. YYYY is the least-significant nibble of the leastsignificant data byte. YYYY is the most-significant nibble of the leastsignificant data byte. n = IMSIZE. Each subsequent byte of data requires 2 wait-syncs + 1 ready-sync + 2 data nibbles. The FWH supports only n=0000 (single-byte) reads. In this clock cycle, the Inel FWH has driven the bus to all ones and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The master (Intel ICH) resumes control of the bus during this cycle.
2
IDSEL
0000 to 1111
IN
3-9
IMADDR
YYYY
IN
10
IMSIZE
0000 (1 byte)
IN
11
TAR0
1111
IN then float
12
TAR1
1111 (float)
Float then OUT OUT
13-14
WSYNC
0101 (WAIT)
15
RSYNC
0000 (READY)
OUT
16 17 17+ 3 x 2n-1 + 2n Previous +1 Previous +1
DATA DATA "DATA"
YYYY YYYY 2 WSYNCS + 1 RSYNC + 2 DATA 1111
OUT OUT OUT
TAR0
OUT then float Float then IN
TAR1
1111 (float)
Note: 1. Field contents are valid on the rising edge of the present clock cycle.
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5.4.1.2.
Single-Byte Read Waveforms
FWH Single-Byte Read Waveforms
Figure 10.
CLK FWH4 FWH[3:0]
STR IDS IMADDR IMS TAR SYNC(3) DATA TAR
5.4.1.3.
Write Cycle Sequence
The firmware hub only supports single-byte writes. Each byte represents either the data to be written or a valid flash command. Refer to the waveforms in Figure 11.
Table 17.
FWH Write Cycle
Clock Cycle 1 Field Name START Field Contents1 FWH[3:0] 1110 FWH[3:0] Direction IN Comments FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitioning high) should be recognized. The START field contents indicate an FWH memory write cycle. Indicates which FWH device should respond. If the IDSEL (ID select) field matches the value ID[3:0], then that particular device will respond to subsequent commands. These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. This size field indicates how many bytes will be transferred during read/write operations. The FWH only supports single-byte writes. This field is the least-significant nibble of the data byte. This data is either the data to be programmed into the flash memory or any valid flash command. This field is the most-significant nibble of the data byte. In this clock cycle, the master (Intel ICH) has driven the bus to all 1s and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The FWH takes control of the bus during this cycle. During the next clock cycle it will be driving the "sync" data. The FWH outputs the values 0000, indicating that it has received data or a flash command.
2
IDSEL
0000 to 1111 YYYY
IN
3-9
IMADDR
IN
10
IMSIZE
0000 (1 byte)
IN
11
DATA
YYYY
IN
12 13
DATA TAR0
YYYY 1111
IN IN then float
14
TAR1
1111 (float)
Float then OUT OUT
15
RSYNC
0000
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Clock Cycle 16
Field Name TAR0
Field Contents1 FWH[3:0] 1111
FWH[3:0] Direction OUT then float
Comments In this clock cycle, the FWH has driven the bus to all 1s and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The master (Intel ICH) resumes control of the bus during this cycle.
17
TAR1
1111 (float)
Float then IN
Note: 1. Field contents are valid on the rising edge of the present clock cycle.
5.4.1.4.
Write Waveforms
Write Waveforms
Figure 11.
CLK FWH4 FWH[3:0]
STR IDS IMADDR IMS DATA TAR SYN C TAR
5.4.1.5.
Response To Invalid Fields
During FWH operations, the Intel FWH will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: * Address out of range: The Intel FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will be decoded by an 8-Mbit FWH. (For a 4-Mbit density, the mostsignificant bit (FWH3) in the third address field also will be ignored.) The Intel FWH will respond to these lower addresses, regardless of the value of the more-significant address bits. Address A22 has the special function of directing reads and writes to the flash core (A22 = 1) or to the register space (A22 = 0). * Invalid IMSIZE field: If the Intel FWH receives an invalid size field during a read or write operation, the internal state machine will reset and no operation will be attempted. The Intel FWH will generate no response of any kind in this situation. Invalid-size fields for a read cycle are anything but 0000. Invalid-size fields for a write cycle are anything but 0000. When accessing register space, invalid field sizes are anything but 0000. * Non-page-aligned address: The Intel FWH assumes that multibyte read addresses are page aligned (i.e., for a 32-byte access, the lower 5 address bits will be zero). If they are not zero, the first byte of data returned by the Intel FWH will correspond to that explicit address, and subsequent data will be as if the first address was indeed page aligned. Once valid START, IDSEL, and IMSIZE fields are received, the Intel FWH always will respond to subsequent inputs as if they were valid. As long as the states of FWH [3:0] and FWH4 are known, the response of the Intel FWH to signals received during the FWH cycle should be predictable. The Intel FWH will make no attempt to check the validity of incoming flash operation commands.
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5.4.1.6.
Abort Operations
FWH4 active (low) indicates either that a START cycle will eventually occur or that an abort is in progress. In either case, if FWH4 is asserted, the Intel FWH will "immediately" tri-state its outputs and the FWH state machine will reset. During a write cycle, there is a possibility that an internal flash write or erase operation is in progress (or has just been initiated). If FWH4 is asserted during this time frame, the internal operation will not abort. The software must send an explicit flash command to terminate or suspend the operation. The internal FWH state machine will not initiate a flash write or erase operation until it has received the last data nibble from the chipset. This means that FWH4 can be asserted as late as this cycle ("cycle 12") and no internal flash operation will be attempted. However, since the Intel FWH will start "processing" incoming data before it generates its SYNC field, it should be considered a non-buffered peripheral device.
5.4.1.7.
Intel FWH Cycle Timing Information
Refer to Figure Figure 12 and Figure 13.
Table 18.
Signal Timing Parameters
Symbol TCHQV TCHQX TCHQZ TAVCH TDVCH TCHAX TCHDX TVSPL TCSPL TPLQZ "PCI Symbol" tval ton toff tsu th trst trst-clk trst-off Parameter CLK to data out CLK to active (float to active delay) CLK to inactive (active to float delay) Input setup time Input hold time Reset active time after power stable Reset active time after CLK stable Reset active to output float delay 7 0 1 100 48 Condition Min. 2 2 28 Max. 11 Units ns ns ns ns ns ms s ns 2 Notes 1 2 2 3 3
Note: 1. 2. Minimum and maximum times have different loads. See the PCI specification. For purposes of active/float timing measurements, the Hi-Z or "off" state is defined as the state where the total current delivered through the component pin is less than or equal to the leakage current specification. This parameter applies to any input type (excluding CLK).
3.
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5.5.
Table 19.
RNG Parameters
RNG Timing Characteristics
# Sym Parameter Write RE = 1 to DWord ready or read DWord to new DWord ready Average sustained throughput Notes 1 1 Typ. 450 13 Max. 1500 50 Unit s s/bit
Note: 1. Table 20. Sampled, not 100% tested. RNG Statistical Characteristics
# Sym B2 AC FOM Parameter Fractional probability of excess 1s Auto correlation coefficient Figure of merit Notes 1,2,3 3 3 7.5 Min. Typ. Max. 316 632 17 Unit 10-6 10-6
Note: 1. Figure 12. Sampled, not 100% tested. Intel FWH Output Timing Parameters
V_th
CLK
V_test T_val
V_tl
FWH[3:0] (Valid Output Data)
FWH[3:0] (Float Output Data)
T_on T_off
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Figure 13.
Intel FWH Input Timing Parameters
V_th
CLK
T_su
V_test
V_tl
T_h
FWH[3:0] (Valid Input Data)
Inputs Valid
V_max
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6.
6.1.
PROM Programming Specifications
Programming ("A/A Mux") Mode Operation
The Intel(R) 82802 is designed to offer a parallel programming mode for faster factory programming. This mode, called the A/A Mux mode, is selected by IC high. The IC pin is pulled down internally in the Intel(R) 82802, so it should be expected that a modest current will be drawn. (See the pin descriptions in Table 1 for further information.) The following information applies only to the Intel(R) 82802 when in the A/A Mux mode. Information regarding the FWH mode (i.e., the standard operating mode) is provided in earlier chapters of this document
6.2.
Bus Operation
All A/A mux bus cycles can be conformed to operate on most automated test equipment and PROM programmers.
6.2.1.
Output Disable/Enable
With OE# at the logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ7 are placed in the high-impedance state. With OE# at the logic-low level (VIL), the device outputs are enabled. Output pins DQ0-DQ7 are placed in the output-drive state.
6.2.2.
Row/Column Addresses
R/C# is the A/A mux control pin used to latch row (A0-A10) and column addresses (A11-A18/4 Mbits, or A[11:19] /8 Mbits). R/C# latches row addresses on the falling edge and column addresses on the rising edge.
6.2.3.
Read Operation
Block information, identifier codes or status register data can be read independently of the VPP voltage. The first task is to write the appropriate read-mode command (Read Array, Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up or after exit from reset, the device defaults to the read array mode. Four control pins dictate the data flow into and out of the component: R/C#, OE#, WE#, and RST#. R/C# is the A/A mux control pin used to latch row and column addresses. OE#, the data output control pin (DQ0-DQ7), drives the selected memory data onto the I/O bus, when active. WE# and RST# must be at VIH.
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6.2.4.
Read Identifier Codes Operation
The read identifier codes operation outputs the manufacturer and device codes (see Table 4). Using the manufacturer and device codes, automated test equipment (ATE) or PROM programmer software can confirm the proper device ID.
6.2.5.
Write Operation
The CUI does not occupy a specific addressable memory location. It is written to when WE# is active and OE# = VIH. The address previously captured by R/C# transitions and the data needed to execute a command are latched on the WE# rising edge.
Table 21.
Bus Operations
Mode Read Output Disable Read Identifier Codes Write Notes 1,2,6 6 3,6 4,5,6 RST# VIH VIH VIH VIH OE# VIL VIH VIL VIH WE# VIH VIH VIH VIL Address X X Note 3 X VPP X X X X DQ[0:7] DOUT High Z Note 3 DIN
Note: 1. 2. 3. 4. 5. 6. When VPP VPPLK, the memory contents can be read, but not altered. X can be VIL or VIH for the control and address input pins and VPPLK or VPPH1/2 for the VPP supply pin. See the DC characteristics for the VPPLK and VPPH1/2 voltages. See Table 4 for the read identifier code data and addresses. Command writes involving block erase or program are reliably executed when VPP = VPPH1/2 and VCC = VCC 0.3 V. Refer to Table 2 for the valid DIN during a write operation. VIH and VIL refer to the DC Characteristics associated flash memory output buffers: VIL min = -0.5V, VIL max = 0.8V and VIH min = 2.0V, VIH max = VCC + 0.5V.
6.3.
Command Definitions
Flash core programming commands in A/A Mux mode are identical to commands for the FWH mode. Refer to Section 4 of this document.
6.4.
Electrical Characteristics in A/A Mux Mode
Certain specifications differ from the previous sections, when programming in the A/A Mux mode. The following subsections provide this data. Any information not provided here is not specific to the A/A Mux mode. Refer to Section 5 of this document and use the Intel FWH mode specifications.
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6.4.1.
Reset Operations
# P1 P2 Symbol tPLPH tPLRH Parameter RST# pulse low time (If RST# is tied to VCC, this specification is not applicable.) RST# low to reset during block erase or program 1, 2 Notes Min. 100 20 Max. Unit ns s
Note: 1. 2. If RST# is asserted when the WSM is not busy (RY/BY# = `1'), the reset will complete within 100 ns. A reset time, tPHAV, is required from the latter of RY/BY# or RST# going high until outputs are valid.
6.4.2.
AC Waveforms for Reset Operations
RY/BY# (R) VIH VIL
P2
RST# (P) VIH VIL
P1
6.4.3.
A/A Mux Read-Only Operations (1,3)
# R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Symbol tAVAV tAVCL tCLAX tAVCH tCHAX tCHQV tGLQV tPHAV tGLQX tGHQZ tQXGH Read cycle time Row address setup to R/C# low Row address hold from R/C# low Column address setup to R/C# high Column address hold from R/C# high R/C# high to output delay OE# low to output delay RST# high to row address setup OE# low to output in low Z OE# high to output in high Z Output hold from OE# high 0 2 2 1 0 50 Parameter Notes Min. 250 50 50 50 50 150 50 Max. Unit ns ns ns ns ns ns ns s ns ns ns
Note: 1. 2. 3. See the AC input/output reference waveform for the maximum allowable input slew rate. OE# may be delayed up to tCHQV - tGLQV after the rising edge of R/C# without affecting tCHQV. Tc = 0 C to + 85 C, 3.3 V 0.3 V VCC
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Figure 14.
A/A Mux Read Timing Diagram
R1 VIH ADDRESSES (A) VIL VIH R/C# (C) VIL VIH OE# (G) VIL R8 VOH DATA (D/Q) VOL VIH WE# (W) VIL VIH RP# (P) VIL
High Z Data Valid
x
Row Address Stable Column Address Stable
x x
Next Address Stable
x
R2 R3 R4
R5 R6 R7
R10 R11
High Z
R9
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6.4.4.
A/A Mux Write Operations (1,2)
# W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 Symbol tPHWL tWLWH tDVWH tWHDX tAVCL tCLAX tAVCH tCHAX tWHWL tCHWH tVPWH tWHGL tWHRL tQVVL Parameter RP# high recovery to WE# low Write pulse width low Data setup to WE# high Data hold from WE# high Row address setup to R/C# low Row address hold from R/C# low Column address setup to R/C# high Column address hold from R/C# high Write pulse width high R/C# high setup to WE# high VPP1,2 setup to WE# high Write recovery before read WE# high to RY/BY# going low VPP1,2 hold from valid SRD, RY/BY# high 0 0 1 1 1 1 1 1 Notes Min. 1 100 50 5 50 50 50 50 100 50 100 150 Max. Units s ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. 2. Refer to Table 6-28 [?] for valid AIN and DIN for block erase or program or other commands. Tc = 0 C to + 85 C, 3.3 V 0.3 V VCC
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Figure 15.
A/A Mux Write Timing Diagram
A VIH ADDRESSES (A) VIL W5 VIH R/C# (C) VIL W1 VIH WE# (W) VIL VIH OE# (G) VIL VOH DATA (D/Q) VOL VIH RY/BY# (R) VIL VIH RP# (P) VIL VPPH1,2 VPP (V) VIL W15 W11 W14 W3 W4 W2 W12 W9 W6 W7 W8 R1 B C1 R2 C C2 D E F
W10
DIN
DIN
W13
Valid SRD
Note: A B C D E F VCC power-up and stand-by Write block erase or program setup Write block erase confirm or valid address and data Automated erase or program delay Read status register data Ready to write another command
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Intel around the world
United States and Canada Intel Corporation Robert Noyce Building 2200 Mission College Boulevard P.O. Box 58119 Santa Clara, CA 95052-8119 USA Phone: (800) 628-8686 Europe Intel Corporation (UK) Ltd. Pipers Way Swindon Wiltshire SN3 1RJ UK Phone: England Germany France Italy Israel Netherlands Sweden (44) 1793 403 000 (49) 89 99143 0 (33) 1 4571 7171 (39) 2 575 441 (972) 2 589 7111 (31) 10 286 6111 (46) 8 705 5600
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